The present invention relates to dynamic random access memories (DRAM), and, more particularly, to the reading of a dynamic random access memory.
As opposed to conventional static random access memories (SRAM) in which the information stored remains indefinitely as long as the memories remain energized, dynamic memories have the particular feature of requiring periodic refreshing of the information stored. Moreover, the reading of a binary data item stored in a dynamic random access memory cell is destructive. Consequently, if one wishes to preserve the data item in the dynamic memory cell after being read, it is necessary to rewrite the data item after this reading.
Conventionally, a dynamic random access memory includes a memory plane organized in matrix fashion into rows and columns of memory cells. A read/write amplifier is connected to the end of each column of the matrix, and a pair of input/output lines (I/O lines) is connected to each read/write amplifier. Moreover, each column of the matrix includes two bit lines. At least one of the bit lines is connected to all the memory cells of the column, and the other bit line serves as a reference. This is particularly so when dealing with memory cells with a transistor.
To read a data item stored in a memory cell of the memory plane, the bit lines of the relevant column are precharged to a common predetermined voltage, such as Vdd/2, for example. Vdd designates the supply voltage of the integrated circuit. The line of memory cells in which the memory cell to be read lies is then selected. If, for example, the data item stored was a logic 1, the bit line connected to the cell then sees its voltage increase with respect to the voltage of the reference bit line.
The read/write amplifier is then selected, and the node of this amplifier connected to the bit line then rises to the voltage Vdd. This is while the node of the amplifier linked to the reference bit line falls to ground. The consequential effect of this is to rewrite the data item to the memory cell.
To output this data item from the memory, the pair of input/output lines is then activated. In other words, the transistors linking this pair of input/output lines to the two above mentioned nodes of the read/write amplifier are rendered to be passing or activated. The voltage difference between the two input/output lines is then equal to the supply voltage Vdd in absolute value. The sign of this voltage difference determines the logic value of the information read.
However, on account of the large potential difference (Vdd) existing between the two input/output lines during the reading of a data item, and also on account of the fact that these input/output lines are relatively long, and consequently, have a relatively high capacitance, a non-negligible current spike occurs during the reading of the data item. This presents a penalty in terms of power consumption.
An object of the present invention is to provide a dynamic random access memory architecture exhibiting a lower current consumption during reading of the memory.
Another object of the present invention is to also increase the information throughput exchanged between the memory and other components, such as a microprocessor connected externally to the memory, for example.
This and other objects, advantages and features in accordance with the present invention are provided by a cache memory cell connected to each read/write amplifier, and is disposed near the read/write amplifier. This cache memory cell is linked to a pair of input/output lines. By disposing the cache memory cell near the amplifier, it is possible when transferring the data item to the cache memory cell via the amplifier to have a large potential difference (e.g., Vdd) only over a short and very weak capacitive metal connection. Consequentlly, this limits the current.
Moreover, this cache memory cell is a static random access memory cell whose content may be read using only a small percentage of the supply voltage (Vdd) of the device. The highly capacitive nature of the input/output lines is, therefore, compensated by the small voltage difference required for reading the data item contained in the cache memory cell.
Stated otherwise, the invention provides a dynamic random access memory device comprising a memory plane including at least one first matrix of memory cells, a read/write amplifier connected to the end of each column of the matrix, and at least one pair of input/output lines associated with the matrix. According to a general characteristic of the invention, the device furthermore comprises at least one cache memory stage connected to each amplifier and disposed in the immediate vicinity of this amplifier. This cache memory stage includes a static random access memory cell connected between the read/write amplifier and the pair of input/output lines.
However, the disposing of a static memory cell or even several cells in parallel in the immediate neighborhood of each read/write amplifier necessitates, in certain architectures in which the room available for disposing the SRAM cell is small, the use of a particularly compact static memory cell with a relatively low number of transistors. Conventional static memory cells generally comprise about 10 or more transistors, including four storage transistors and three precharge transistors. It then turns out to be impossible to install such a static memory cell when the space available at the foot of a read/write amplifier is small.
The invention advantageously provides a static random access memory cell including a very small number of transistors, and in particular, two storage transistors. This is done in the likeness of cache memory cell. However, with such a particularly compact static memory cell, there is a risk of losing the data item stored in this cell on account of leakage currents inherent to any transistor. It is for this reason that it is then necessary for the cache memory stage to also contain retention means for maintaining in the static memory cell a binary data item, that has been previously transferred thereto from a memory cell of the memory plane via the amplifier.
In one embodiment, a cache memory stage includes a static random access memory cell. The static random access memory cell comprises two storage transistors, and a pair of first access transistors connected between the amplifier and the storage transistors, a pair of second access transistors respectively connected between the pair of input/output lines and the storage transistors. Retention means maintains in the static memory cell a binary data item that had been previously transferred thereto from a memory cell via the amplifier.
In one embodiment, there is provision for the second access transistors to have larger leakage currents than the other transistors of the static memory cell. The retention means then includes the second access transistors. This embodiment is particularly compact. Several possibilities are offered for obtaining larger leakage currents in certain transistors than in others. Among these possibilities, those which will be mentioned now, may be used alone or in combination.
More precisely, a first possibility is with respect to the transistors which should exhibit the larger leakage currents. The transistors may include a channel length and a gate oxide thickness which are smaller than the channel length and the gate oxide thickness of the other transistors of the static memory cell.
As a variation, the retention means may apply different predetermined bias voltages at certain terminals of each transistor to obtain a larger leakage current. Stated otherwise, the transistors which exhibit a larger leakage current are directly acted on by increasing their leakage current by applying different predetermined bias voltages at certain terminals of these transistors.
Another possibility for embodying the retention means includes applying a substrate effect to each transistor of the static memory cell, with the exception of those transistors which one wishes should exhibit a larger leakage current. Thus, this characteristic is obtained by decreasing the leakage currents of the other transistors of the static memory cell by applying a substrate effect to these other transistors. In other words, different predetermined bias voltages are applied to the substrate and to the source of these transistors.
To increase the throughput of the dynamic random access memory device according to the invention, there is advantageously a provision for at least two cache memory stages to be connected respectively in parallel to each amplifier. Thus, for example, while reading a data item contained in a cache memory stage, it is possible to transfer a data item from a memory cell of the memory plane to the other cache memory stage.
The present invention is also directed to a process for reading a data item stored in a memory cell of the memory plane as defined above. The process includes transferring the data item to the static random access memory cell of the cache memory stage associated with the column containing the memory cell, then the content of the static memory cell is read via the input/output lines.